• Efficient on-chip accelerator interfaces to reduce software overhead , U.S. Patent Number 7,827,383.

• Low overhead access to shared on-chip hardware accelerator with memory-based interfaces, U.S. Patent Number 7,809,895.

• Enabling on-chip features via efuses , U.S. Patent Number 7,795,899.

• Efficient caching of stores in scalable chip multi-threaded systems , U.S. Patent Number 7,793,044.

• Missing store operation accelerator , U.S. Patent Number 7,757,047.

• Accelerating cryptographic hash computations , U.S. Patent Number 7,599,489.

• Efficient on-chip instruction and data caching for chip multiprocessors, U.S. Patent Number 7,543,112.

• Hardware-based technique for improving the effectiveness of prefetching during scout mode, U.S. Patent Number 7,529,911.

• Method and structure for pipelining of SIMD conditional moves, U.S. Patent Number 7,480,787.

• Execution displacement read-write alias prediction, U.S. Patent Number 7,434,031.

• Prefetch prediction, U.S. Patent Number 7,434,004.

• Software-based technique for improving the effectiveness of prefetching during scout mode, U.S. Patent Number 7,373,482.

• Method and apparatus for alleviating register window size constraints, U.S. Patent Number 7,013,377.

• Method for rapid interpretation of results returned by a parallel compare instruction, U.S. Patent Number 7,003,653.

• Checksum determination using parallel computations on multiple packed data elements, U.S. Patent Number 5,960,012.

Last updated: August 2011